`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:00:38 08/09/2012 
// Design Name: 
// Module Name:    siete_segmentos 
// Project Name: 
// Target Devices:  mmmmmmmmmmmmmmmaaaaaaaaaaaaaaggggggggggggggggggiiiiiiiiiiiiiiiiiaaaaaaaaaa
//akljsdfh 
Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module siete_segmentos(busEntrada, busSalida
    );
input [3:0] busEntrada;
output reg [7:0] busSalida;
   always @*
         case (busEntrada)
            4'b0000  : busSalida <= 8'b10000001;
            4'b0001  : busSalida <= 8'b11001111;
            4'b0010  : busSalida <= 8'b10010010;
            4'b0011  : busSalida <= 8'b10000110;
            4'b0100  : busSalida <= 8'b11001100;
            4'b0101  : busSalida <= 8'b10100100;
            4'b0110  : busSalida <= 8'b10100000;
            4'b0111  : busSalida <= 8'b10001111;
            4'b1000  : busSalida <= 8'b10000000;
            4'b1001  : busSalida <= 8'b10000100;
            4'b1010  : busSalida <= 8'b10001000;
            4'b1011  : busSalida <= 8'b11100000;
            4'b1100  : busSalida <= 8'b10110001;
            4'b1101  : busSalida <= 8'b11000010;
            4'b1110  : busSalida <= 8'b10110000;
            4'b1111  : busSalida <= 8'b10110000;
            default  : busSalida <= 8'b10000000;				
         endcase
endmodule
